In general, realizing a good characteristic of cell transistors is very important in manufacturing a memory device such as a DRAM (dynamic random access memory).
However, as semiconductor devices have become increasingly highly integrated, the line width of the design rule has become further decreased and, thus, the gate line width of a transistor has also decreased. Accordingly, short channel effects such as a punch-through phenomenon and a severe fluctuation in threshold voltage (Vth) have arisen, which make it more difficult to achieve sufficient quality in the characteristics of a transistor.
Conventionally, a pocket ion implantation scheme is utilized in manufacturing a transistor in order to reduce the short channel effects. In the pocket ion implantation scheme, a lightly doped drain (LDD) region is formed to an end of a source and/or drain, and the substrate concentration only around the LDD region is higher than at the channel.
Such a conventional manufacturing method for a transistor will hereinafter be described in detail with reference to FIG. 1A to FIG. 1C.
As shown in FIG. 1a, a gate insulating layer 11 and a gate 12 are sequentially formed on a P-type semiconductor substrate 10. A relatively thin screen oxide 13 is formed on the gate 12 and on a surface of a substrate 10.
The screen oxide 13 acts as a protective layer to prevent damage of the substrate 10 in a later process of ion implantation.
Subsequently, P-type pocket regions 14a and 14b are formed in the substrate 10 on opposite sides of the gate, by implanting P-type impurity ions 14 in a direction which is slanted with respect to the surface of the substrate 10 (i.e., in a direction which is not perpendicular to the surface of the substrate).
Then, as shown in FIG. 1B, low concentration N-type impurity ions 15 are implanted in a direction vertical to the substrate 10, such that N-type LDD regions 15a and 15b are formed on the substrate 10 on opposite sides of the gate 12.
Subsequently as shown in FIG. 1C, the screen oxide 13 is removed, and a spacer 100 is formed on the substrate 10 and the gate 12. In more detail, the spacer 10 is formed on side walls of the gate 12 by sequentially depositing a first oxide layer 16, a nitride layer 17, and a second oxide layer 18 and then etching them back such that an uppermost portion of the gate 12 may become exposed.
The first and the second oxide layers 16 and 18 may be formed as a tetraethyl orthosilicate (TEOS) layers. The nitride layer 17 may be formed as a silicon nitride (SiN) layer. The first oxide layer 16 acts as a buffer layer for alleviating stress on the nitride layer 17.
Subsequently, high concentration N-type impurity ions 19 are implanted in a direction vertical to the substrate 10, such that N-type source/drain junction regions 19a and 19b are formed in the substrate 10 on opposite sides of the spacers 100.
Since the integration of semiconductor devices has been highly accelerated, the gate length has become very short, (e.g., as short as about 70 nm under the 90 nm rule), and, therefore, the profile of the pocket regions 14a and 14b under the gate 12 are becoming more important.
For effectively limiting short channel effects such as punch-through and severe fluctuation of the threshold voltage, the pocket regions 14a and 14b should be configured to have more depth under the gate 12 than in other regions, (e.g., by increasing the impurity concentration in the pocket regions 14a and 14b).
However, when the impurity concentration of the pocket region 14a and 14b is increased, the junction capacitance also increases, thereby deteriorating the operation speed of the resulting semiconductor device. Accordingly, it is difficult to realize a high speed device.